Support for Western Digital RISC-V SweRV Core and OmniXtend cache-coherent interconnect announced - ELE Times
SweRV - An Annotated Deep Dive | Electronics etc…
SweRV: Western Digital legt eigene RISC-V-Designs offen - Golem.de
GitHub - westerndigitalcorporation/swerv-ISS: Western Digital's Open Source RISC-V SweRV Instruction Set Simulator
PCHardCores: Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative
Everything needed to deploy a Western Digital EH1 superscalar RISC-V core
Western Digital Rencana Open Source RISC-V SweRV Core Baru
Western Digital Delivers New SweRV Core RISC-V Processor - FunkyKit
Western Digital's RISC-V "SweRV" Core Design Released For Free
Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores - RISC-V International
Risc-V day: Western Digital SweRV Core
Three New Western Digital RISC-V Developments Revealed! | Tech ARP
Western Digital's Long Trip from Open Standards to Open Source Chips | Data Center Knowledge
Western Digital RISC-V SweRV Core is now on GitHub | Packt Hub
Codasip SweRV Core Support Package | Codasip
What is SweRV Core EH2? | Codasip
SweRV core roadmap white paper | Flash Memory | Arm Architecture
Western Digital will open source SweRV RISC-V CPU designs and tools - TechRepublic
Western Digital: SweRV ist ein SSD-Controller mit RISC-V-Architektur - ComputerBase
CHIPS Alliance to curate building blocks for RISC-V chips
