Western Digital's Long Trip from Open Standards to Open Source Chips | Data Center Knowledge | News and analysis for the data center industry
Western Digital Takes A RISC
RISC-V | Western Digital | Western Digital
Western Digital's RISC-V "SweRV" Core Design Released For Free
RISC-V | Western Digital | Western Digital
Western Digital NAS Powered by SiFive Microsemi and RISC-V
Western Digital's RISC-V 'Swerv' Core Now Available for Free - ExtremeTech
RISC-V | Western Digital
RISC-V: Too Open to Succeed - Embedded Computing Design
Key Takeaways from the 2019 RISC-V Summit - ServeTheHome
RISC-V Enables Smart Storage Devices
RISC-V | Western Digital
Three New Western Digital RISC-V Developments Revealed! | Tech ARP
An Introduction to SweRV, a RISC-V Core - Industry Articles
Western Digital Releases Their RISC-V Cores To The World | Hackaday
Western Digital NAS Powered by SiFive Microsemi and RISC-V
CHIPS Alliance announces updated RISC-V SweRV cores
Western Digital Made RISC-V Linux & BusyBox Boot on Sipeed Maix Go Board - CNX Software
Western Digital Announces New Open Solutions, Including a RISC-V Core - Embedded Computing Design
RISC-V | Western Digital
Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms
Western Digital Releases Fedora Desktop on RISC-V Tutorial - AB Open
Key Takeaways from the 2019 RISC-V Summit - ServeTheHome
RISC-V | Western Digital
